Many advanced application programs (applications) such as the compression of video data, which are intended to run on mobile communication terminals, require relatively high computation power. The required computation power is often greater than the available computation power of modern so-called embedded microprocessing units (MPU). However, many modern mobile communication terminals contain baseband chips, on which two or more processors are integrated for different tasks, and which are each assigned to respective processors. Many of these tasks are not active at the same time, so that the maximum possible performance of the system is often not exploited when running applications.
The effectively available computation power thus represents a relatively low lower limit for applications that are to be run on a mobile communication terminal. One possible way to solve the problem is to use dedicated hardware accelerators, which are able to process specific applications with higher performance. However, this solution is not sufficiently flexible, since it requires a specific hardware design for each application that is to be sped up. Another possibility for speeding up the running of applications in mobile communication terminals is to use a dedicated external high-power MPU. However, this solution is generally highly costly, since it likewise requires additional external use of hardware.
Complex embedded system applications nowadays use chips that comprise a number of microprocessors, on-chip memory elements and coprocessors. The combination of processor cores and memory elements on the same chip allows effective utilization of the chip area. A distinction is drawn in the chip between the instruction cache, the data cache and on-chip SRAM. The instruction and data cache memories are high-speed local memories, which form an interface between the processor and the off-chip memory.
Mobile communication terminals with higher functionality, such as smartphones, generally have two main processors, specifically a modem processor or modem controller, and an application processor. A digital signal processor (DSP) is also always provided, and is generally combined with the modem controller, being referred to as a baseband chip set (GSM+protocol, thus corresponding (for example) to DSP+mC). As a result of the addition of the application programs to be processed, subdivision into a baseband chip set and an application processor was necessary, in which the application processor, which is also often referred to as a coprocessor, has to process all the application programs.
The publication “Developing Embedded Software in Multi-Core SoCs” from the British company Chip-Design-Firma ARM Ltd. (Author: Paul Kimelman) describes a very wide range of configurations and applications of multiprocessor systems in the field of embedded processor cores. These applications relate essentially to real-time requirements for the various tasks, for example, in a mobile communication terminal. The publication then proposes suitable hardware architectures and discusses their performance on the basis of these requirements.